1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and specifically relates to a technique for enhancing a high breakdown voltage of a MOS transistor.
2. Description of the Related Art
As a semiconductor device is given a higher power and a higher performance, a number of elements such as transistors arranged on a semiconductor device is dramatically increasing in the recent years, and reduction and fining in size are being required. This does not leave a transistor in which a high breakdown voltage is required, such as a liquid crystal driver, an exception thereof.
In reducing the size of the transistor, a gate oxide film has been thinned so that a so-called short channel effect does not occur. However, by thinning the gate oxide film, an electric field (gate electric field) concentrates at a portion where a gate electrode and a drain overlap, and, due to this high electric field, a problem of an increase of leakage current (GIDL: Gate Induced Drain Leakage) caused by electrons tunneling from a valence band to a conductive band is being manifested.
As a method for solving the aforesaid problem, conventionally, a technique to lower the electric field of edge portions of the gate electrode by making a thickness of the gate oxide film located below the edge portions of the gate electrode thicker than that above a channel area has been employed (offset LOCOS). However, in this method, a configuration thereof has the edge portions of the gate electrode arranged above a LOCOS oxide film that is thicker than the gate oxide film, and as such, the element as a whole requires a very large occupying space.
To solve the problem above, a technique described in Japanese patent application publication No. 2004-47721 (hereinafter referred to as ‘document 1’) has been proposed. In this technique, as shown in FIG. 8, an offset area w1 is provided to separate a high concentration drain area 73 and a silicide 81 from a gate electrode 76 in a MOS transistor, to alleviate the electric field between the drain area 73 and a drain side edge portion of the gate electrode 76, to thereby realize a reduction in the leakage current and an enhancement of the breakdown voltage.
Note that in FIG. 8, 71 indicates an element separating insulation film, 72 indicates a drift area, 73 indicates the drain area, 74 indicates a source area, 75 indicates the gate oxide film, 76 indicates the gate electrode, 77, 78 indicate insulation films and 81 to 83 indicate silicide areas.
However, even in the technique of the document 1, the offset area w1 needs to be secured, and as such, a size enlargement in accordance with said offset is inevitable; and this hinders the size reduction of the transistor.